1. Field of the Invention
The present invention relates to a method and a device for driving an AC type plasma display panel.
A plasma display panel (a PDP) unites high speed and high resolution suitable for a television set as well as a computer monitor and is used as a large screen display device. As it comes into wide use, its using environment becomes diversified. Therefore, a driving method is desired that realizes a stable display insusceptible of temperature variation or voltage regulation of a power source. It is also an important subject to reduce power consumption.
2. Description of the Prior Art
As a color display device, a surface discharge format AC type PDP is commercialized. The surface discharge format means a structure in which display electrodes (first electrodes and second electrodes) that are anode and cathode in display discharge for securing luminance are arranged on a front or a back substrate in parallel, and address electrodes (third electrodes) are arranged so as to cross the display electrode pairs. There are two forms of display electrode arrangement. In the first form, a pair of display electrodes is arranged for one row of a matrix display. In the second form, the first display electrode and the second display electrode are arranged alternately at a constant pitch, so that each display electrode except both ends of the arrangement works for two rows (lines) of a display. Regardless of the arrangement form, the display electrode pairs are covered with a dielectric layer.
In a display using a surface discharge format PDP, one of the two display electrodes corresponding to a row (the second electrode) is used as a scan electrode for selecting a row, so as to generate address discharge between the scan electrode and the address electrode, which causes address discharge between the display electrodes. Thus, electrostatic charge quantity in the dielectric layer (wall charge quantity) is controlled in accordance with contents of a display in addressing. After the addressing, a sustaining voltage Vs having alternating polarities is applied to the display electrode pair. The sustaining voltage Vs satisfies the following inequality (1).
VfXYxe2x88x92VwXY less than Vs less than VfXYxe2x80x83xe2x80x83(1)
Here, VfXY denotes a discharge start voltage between the display electrodes, and VwXY denotes the wall voltage between the display electrodes.
When the sustaining voltage Vs is applied, a cell voltage (the sum of a driving voltage that is applied to the electrode and the wall voltage) exceeds the discharge start voltage VfXY and surface discharge is generated on the surface of the substrate only in cells having a predetermined quantity of wall charge. As the application period is shortened, light emission looks as if it is continuous.
A discharge cell of a PDP is basically a binary light emission element. Therefore, a half tone is reproduced by setting integral light emission quantity of each discharge cell in a frame period in accordance with a gradation value of input image data. A color display is one type of a gradation display, and a display color is determined by combining luminance values of three primary colors. The gradation display is realized by making one frame of plural subframes (or subfields in an interlace display) having luminance weights and by setting the integral light emission quantity combining on and off of the light emission for each subframe.
FIG. 9 is a diagram of voltage waveforms showing a general driving sequence. In FIG. 9, reference letters X, Y and A denote the first display electrode, the second display electrode and the address electrode, respectively. Suffixes 1xe2x88x92n of X and Y denote arrangement orders of rows corresponding to display electrodes X and Y. Suffixes 1xe2x88x92m of A denote arrangement orders of columns corresponding to address electrodes A.
A subframe period Tsf assigned to each subframe is divided into a reset period TR for equalizing charge distribution in a screen, an address period TA for forming the charge distribution corresponding to contents of a display by applying a scan pulse Py and an address pulse Pa and a sustain period (or a display period) TS for securing a luminance value corresponding to a gradation value by applying a display pulse Ps. The lengths of the reset period TR and the address period TA do not change regardless of the luminance weight, while the length of the sustain period TS is longer as the luminance weight is larger. The driving sequence is repeated for each subframe in the order of the reset period TR, the address period TA and the display period TS.
When the sustain period of each subframe finishes, there are discharge cells having relatively much wall charge and discharge cells having little wall charge. In order to increase reliability of the addressing of the next subframe, a reset process for charge equalization is performed in the reset period TR.
U.S. Pat. No. 5,745,086 discloses a reset process in which a first ramp voltage and a second ramp voltage are applied to a discharge cell sequentially. When a ramp voltage having a mild gradient (an increasing waveform voltage) is applied, light emission in the reset process is made minute so as to prevent a contrast from dropping because of the characteristics of microdischarge as explained below. In addition, the wall voltage can be set to any target value regardless of variation of a cell structure.
If the gradient of the ramp voltage is mild, minute charge adjustment discharges are generated plural times in the rising process of the applied voltage. When the gradient is made milder, discharge intensity is reduced and a discharge period is shortened so that the discharge transfers to a continuous discharge form. In the following explanation, periodical charge adjustment discharge and continuous charge adjustment discharge are collectively called xe2x80x9cmicrodischargexe2x80x9d.
In the microdischarge, the wall voltage can be controlled by setting the maximum final voltage of the ramp waveform. During the microdischarge, even if the cell voltage Vc (i.e., the wall voltage Vw plus an applied voltage Vi) that is applied to a discharge space exceeds discharge start threshold level (hereinafter, denoted by Vt) because of increase of the ramp voltage, the cell voltage is always maintained in the vicinity of the voltage Vt thanks to the generation of microdischarge. The microdischarge reduces the wall voltage by the same amount as the increase of the ramp voltage. Supposing the final value of the ramp voltage is Vr, and the wall voltage is Vw when the ramp voltage reaches the final value Vr, the following equation is satisfied since the cell voltage Vc is kept at Vt.
Vc=Vr+Vw=Vt, therefore
Vw=xe2x88x92(Vrxe2x88x92Vt)
Since the voltage Vt has a constant value determined by electric characteristics of the discharge cell, the wall voltage can be set to any desired value by setting the final value Vr of the ramp voltage. More specifically, even if there is a minute difference in the voltage Vt between the discharge cells, the difference between the voltages Vt and Vw of each of all discharge cells can be equalized.
In the example shown in FIG. 9, the first ramp voltage ascending to a voltage Vyr1 is applied to the display electrode Y, so that wall charge is formed between the display electrode X and the display electrode Y (referred to as interelectrode XY) as well as between the display electrode Y and the address electrode A (referred to as interelectrode AY). After that, the second ramp voltage descending to a voltage Vyr2 is applied to the display electrode Y, so that the wall voltage at the interelectrode XY and the wall voltage at the interelectrode AY get close to a target value. In synchronization with the application of the ramp voltage, potentials Vxr1 and Vxr2 are applied to the display electrode X. The application of a voltage means to bias an electrode so as to generate a predetermined voltage between the electrode and a reference potential. The voltage values Vxr1 and Vyr1 are selected so that microdischarge is generated at the second ramp voltage without fail.
After this reset process, the addressing is performed. In the address period TA, all the display electrodes Y are biased to a non-selection potential Vya2 at the start point, and then display electrodes Y corresponding to selected row i (1xe2x89xa6ixe2x89xa6n) are biased temporarily to a selection potential Vya1 (application of the scan pulse). In synchronization with the row selection, the address electrodes A are biased to the selection potential Va only in the columns of the selected row, to which the selected cells that generate address discharge belong (application of the address pulse). The address electrode A of a column to which the non-selected cells belong is set to the reference potential (usually zero volts). The display electrode X is biased to a constant potential Vxa from the start to the end of the addressing regardless of whether the row is a selected row or a non-selected row. In the sustain period TS, the display pulse Ps having the amplitude Vs is applied to the display electrode Y and the display electrode X alternately. The number of application times is substantially proportional to the luminance weight.
In the conventional method, the voltage Vyr2 that is applied to the display electrode Y during the reset period TR is the same as the selection voltage Vya1 that is applied in the address period TA, and a common power source is used for applying the two voltages. Furthermore, the voltage Vxr2 that is applied to the display electrode X during the reset period TR is the same as the bias voltage Vxa in the address period TA.
FIG. 10 is a timing chart of addressing in the conventional method. In FIG. 10, the time relationship between the scan pulse for the j-th row (line) and the address discharge is illustrated. The row selection potential is Vya1, the row non-selection potential is Vya2, the address selection potential is Va and the address non-selection potential is a reference potential (e.g., zero volts).
When the scan pulse is applied to the display electrode Y corresponding to the j-th row, and the address voltage Va is applied to the address electrode A, address discharge is generated at the interelectrode AY. At the same time substantially, address discharge is generated also at the interelectrode XY, so that wall charge is formed inside the cell. In other words, a wall voltage Vwxyxe2x88x92a is generated at the interelectrode XY with respect to the negative display electrode X.
The address discharge becomes the maximum after a time tpeak delay from the start of the scan pulse application and finishes when a time tend passes. The lengths of the time tpeak and the time tend depend on contents of the display and the address voltage Va and are affected by a panel temperature and variation of the cell structure.
In the conventional method, the address voltage Va is set to a value of approximately 70 volts, and the time tend is approximately 2 microseconds. The driving process requires a time td2 for resetting the electrode to the non-selection potential after the address discharge is finished. If a common circuit device is used, the time td2 is 0.2 microseconds, and time necessary for addressing one row (i.e., an address cycle) Tacxe2x80x2 is 2.2 microseconds.
For example, supposing the number of rows of a display screen is 500, the number of subframes is 10 and time necessary for a reset process of one subframe is 300 microseconds, the total sum of the reset period and the address period of one frame becomes (300+2.2xc3x97500)xc3x9710=14000 microseconds (=14 milliseconds). Since a frame period of a full motion picture is approximately 16.7 milliseconds, time that can be assigned to the sustain period is approximately 2.7 (=16.7xe2x88x9214) milliseconds.
If the reset period is shortened and the sustain period is elongated so as to increase luminance of a display, the charge cannot be equalized sufficiently, resulting in an unstable display. If the address cycle Tacxe2x80x2 is shortened, application of the address voltage should be finished before the address discharge finishes. As a result, the wall voltage Vwxyxe2x88x92a after the address discharge becomes insufficient, which makes a display unstable. In addition, if the address voltage Va is raised for shortening the address cycle Tacxe2x80x2, power consumption in the addressing increases.
An object of the present invention is to shorten the time necessary for addressing without deteriorating stability of a display. Another object is to reduce power consumption in addressing.
According to the present invention, a method comprises the steps of applying an increasing waveform voltage between a reference potential line and a scan electrode so as to perform a reset process in which charge is equalized in all cells before addressing, and applying a selection voltage Vya1 having the same polarity as a final applied voltage Vyr2 in a reset process and being higher (an absolute value is larger) than the voltage Vyr2 by a potential difference xcex94Vy between the scan electrode corresponding to a selected row and the reference potential line in the addressing.
In the conventional driving method, the voltage Vya1 is equal to the voltage Vyr2. Therefore, if an amplitude of the scan pulse is changed, the voltage Vyr2 also changes. Accordingly, it is found that even if the selection voltage Vya1 is increased, the address cycle Tac cannot be shortened. In order to explain this, threshold level voltages at which microdischarge can be generated at the interelectrode XY and the interelectrode AY are supposed to be Vtxy and Vtay, and cell voltages are supposed to be Vcxy and Vcay. Also, applied voltages are supposed to be Vrxy and Vray.
After the microdischarge starts, even if the applied voltages Vrxy and Vray are increased, the cell voltages Vcxy and Vcay are maintained to be equal to the threshold level voltages Vtxy and Vtay, respectively.
In a period while the increasing waveform voltage is applied and microdischarge is generated, the following equations are satisfied.
Vtxy=Vrxy+Vwxy
Vtay=Vray+Vway
Vwxy and Vway denote wall voltages at the interelectrode XY and the interelectrode AY.
When the applied voltage of the display electrode Y reaches Vyr2 while the voltage Vxr2 is applied to the display electrode X and the address electrode A is biased to the reference potential, the following equations are satisfied.
Vcay=Vyr2+Vway=Vtay
Vcxy=Vyr2+Vxr2+Vway=Vtxy
After that, in the address period, when the selection voltage Vya1 (=Vyr2) is applied to a certain display electrode Y, the address voltage Va is applied to an address electrode A, and the voltage Vxa(=Vxr2) is applied to a display electrode X, the following equations are satisfied.
Vcay=Vyr2+Vway+Va=Vtay+Va
Vcxy=Vyr2+Vxr2+Vway=Vtxy
In this case, even if the voltages at the interelectrode AY and the interelectrode XY are raised, the voltage at the discharge gap does not change at all since Vcay=Vtay+Va, and Vcxy=Vtxy. Therefore, as mentioned above, the address cycle Tac is not shortened.
On the contrary, according to the present invention, as shown in FIG. 1, in the reset period TR, the display electrode Y is supplied with the increasing waveform voltage that reaches the voltage Vyr2 at the end of the reset period TR, and the display electrode X is supplied with the voltage Vxr2. Then, in the address period TA, the display electrode Y corresponding to the selected row is supplied with the selection voltage Vya1 that is higher than the voltage Vyr2 by the potential difference xcex94Vy. The polarity of the potential difference xcex94Vy is selected so that the potential differences at the interelectrode XY and the interelectrode AY are increased.
The potential Vxa of the display electrode X in the address period TA is set to a value equal to the voltage Vxr or a value that is the voltage Vxr plus the potential difference xcex94Vx such that the potential difference at the interelectrode XY increases. In addition, the potential of the address electrode A in the address period TA is set to the same value as that at the end of the reset period TR.
In this case, in the address period TA, when the display electrode Y corresponding to the selected row is supplied with the selection voltage Vya1 (=Vyr2+xcex94Vy), the address electrode A is supplied with the address voltage Va, and the display electrode X is supplied with the bias voltage Vxa(=Vxr2+xcex94Vx), the following equations are satisfied.
Vcay=Vtay+Va+xcex94Vy
xe2x80x83Vcxy=Vtxy+xcex94Vy+xcex94Vx
According to the driving method of the present invention, the cell voltages Vcay and Vcxy that are applied to discharge gaps of the interelectrode AY and the interelectrode XY become higher than the conventional method by potential differences xcex94Vy and xcex94Vy+xcex94Vx, respectively. Thus, the time tpeak and the time tend for the address discharge shown in FIG. 2 can be shortened compared to the conventional method.
Here, the relationships between the potential difference xcex94Vy and the time tpeak as well as the time tend, which are measured with the potential difference xcex94Vx as a parameter, are shown in FIG. 3. It is found that the delay time of the address discharge increases if the value of the potential difference xcex94Vy is increased too much, though the delay time of the address discharge is shortened if the value of the potential difference xcex94Vy is increased appropriately. It is also found that the value of the potential difference xcex94Vx affects the delay time of the address discharge less than the potential difference xcex94Vy does, so the potential difference xcex94Vx can be zero. The relationships between the potential difference xcex94Vy and the time tpeak as well as the time tend when the potential difference xcex94Vx is zero are shown in FIG. 4.
As shown in FIG. 4, it is understood that a stable fast addressing can be performed when the potential difference xcex94Vy is set to a value within the range of 10-35 volts for shortening the delay time of the address discharge. It is understood from FIG. 4 that when 10 volts less than xcex94Vy less than 35 volts, the time tend from the leading edge of the pulse to the end of the address discharge is approximately 0.8-1.2 microseconds.
In real drive, it is desirable to set the address cycle Tac in prospect of the time td2 necessary for resetting the electrode potential to the non-selection state as shown in FIG. 2. However, it is not always necessary to reset the electrode potential after the address discharge finishes completely. A time point close to the end of the address discharge can be used as the trailing edge of the pulse without affecting the stability of the display substantially.
From the above-mentioned facts, stable addressing can be performed under the condition of xcex94Vx=0 volts, 10 volts less than xcex94Vy less than 35 volts, and 0.8 microseconds less than Tac less than 1.4 microseconds. Since the address cycle Tac is shortened compared to the conventional method, the shortened portion can be assigned to the sustain period, so that the number of display discharge times can be increased and the luminance can be raised.
The present invention has another effect. FIG. 5 is a graph showing a margin of the address voltage Va. A stable display can be obtained by setting the voltage Va to a value within the range between two thick lines in FIG. 5. It is understood from FIG. 5 that the voltage Va should be set to a value within the range of 30-50 volts when the potential difference xcex94Vy is in the range of 10-35 volts as mentioned above. Compared to the conventional method in which the address voltage Va is set to approximately 70 volts, power consumption in the address period can be reduced substantially.